Design of Optimal Elliptic Curve Cryptography by using Partial Parallel Shifting Multiplier with Parallel Complementary
Keywords:Elliptic Curve Cryptography (ECC), Look-Up Table (LUT), Parallel Shifting Multiplier, Parallel Complementary Method, Private Key, Public Key, Vedic Multiplier (VM)
AbstractHigh-speed Elliptic Curve Cryptography (ECC) modules implementation with less time, area, devices used is the recent research studies in cryptographic technology. The inclusion of modulus function in ECC contains several computations that lead to more time consumption and less speed. More multipliers and dividers utilization in ECC-based encryption/decryption required huge logic gates and registers. Hence, area and power consumption are more in ECC hardware unit. To overcome these problems, an enhanced ECC proposed in this paper. The framework optimizes the size of the multiplier and divider leads to a reduction of logic gates utilization. In our proposed work, we present a novel design structure for multiplier and divider based on ECC model defined by . During the encryption, the self-multiplication of the input data for n number of times creates the public key. The remainder obtained from modulo division is regarded as the corresponding encrypted form of input data. To perform these multiplication and modulo division, we present a novel Partial Parallel Shifting Multiplier (PPSM) and Parallel Complementary Method (PCM) to reduce the number of logic gates and improve the operational speed. The comparative analysis between the proposed (PPSM-PCM) with the existing ECC architectures regarding the parameters such as number of logic gates, LUTs, FFs, frequency, power consumption, delay rate and latency assures the suitability of high-speed ECC in real-time applications.
R. Aneesh and S. K. Mohan, "Design and Analysis of High Speed, Area Optimized 32x32-Bit Multiply Accumulate Unit Based on Vedic Mathematics," in International Journal of Engineering Research and Technology, 2014.
T. Pöppelmann and T. Güneysu, "Towards efficient arithmetic for lattice-based cryptography on reconfigurable hardware," in Progress in Cryptology–LATINCRYPT 2012, ed: Springer, 2012, pp. 139-158.
M. Morales-Sandoval, C. Feregrino-Uribe, P. Kitsos, and R. Cumplido, "Area/performance trade-off analysis of an FPGA digit-serial GF (2m) Montgomery multiplier based on LFSR," Computers & Electrical Engineering, vol. 39, pp. 542-549, 2013.
L. K. I. Maglogiannis, K. Delakouridis, and S. Had-jiefthymiades, "Enabling location privacy and medical data encryption inpatient telemonitoring systems," IEEE Transactions on Informational Technology and Biomedicals, vol. 13, pp. 946-954, 2009.
S. K. Sahu and M. Pradhan, "Implementation of Modular multiplication for RSA Algorithm," in International Conference on Communication Systems and Network Technologies (CSNT), 2011 2011, pp. 112-114.
R. Bhaskar, G. Hegde, and P. Vaya, "An efficient hardware model for RSA Encryption system using Vedic mathematics," Procedia Engineering, vol. 30, pp. 124-128, 2012.
J. Adikari, V. S. Dimitrov, and L. Imbert, "Hybrid Binary-Ternary Number System for Elliptic Curve Cryptosystems," IEEE Transactions on Computers, vol. 60, pp. 254-265, 2011.
R. Azarderakhsh and A. Reyhani-Masoleh, "Efficient FPGA Implementations of Point Multiplication on Binary Edwards and Generalized Hessian Curves Using Gaussian Normal Basis," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, pp. 1453-1466, 2012.
C. Rebeiro, S. S. Roy, and D. Mukhopadhyay, "Pushing the limits of high-speed GF (2 m) elliptic curve scalar multiplication on FPGAs," in Cryptographic Hardware and Embedded Systems–CHES 2012, ed: Springer, 2012, pp. 494-511.
P. Sasdrich and T. Güneysu, "Efficient Elliptic-Curve Cryptography using Curve25519 on reconfigurable devices," Reconfigurable Computing: Architectures, Tools, and Applications, vol. 8405, pp. 25-36.
C. H. Tseng, S.-H. Wang, and W.-J. Tsaur, "Hierarchical and Dynamic Elliptic Curve Cryptosystem Based Self-Certified Public Key Scheme for Medical Data Protection," IEEE Transactions on Reliability, vol. 64, pp. 1078-1085, 2015.
S. S. Roy, C. Rebeiro, and D. Mukhopadhyay, "Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, pp. 901-909, 2013.
G. G. Kumar and V. Charishma, "Design of high-speed Vedic multiplier using Vedic mathematics techniques," International Journal of Scientific and Research Publications, vol. 2, p. 1, 2012.
A. Haveliya, "FPGA implementation of a Vedic convolution algorithm," International Journal of Engineering research and applications, vol. 2, pp. 678-884, 2012.
S. R. Huddar, S. R. Rupanagudi, M. Kalpana, and S. Mohan, "Novel high-speed Vedic mathematics multiplier using compressors," in International Multi-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s), 2013 2013, pp. 465-469.
J. Subudhi and C. Karthick, "Implementation of the Vedic divider on RSA cryptosystem," in International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS), 2015, 2015, pp. 1-5.
R. Bathija, R. Meena, S. Sarkar, and R. Sahu, "Low Power High Speed 16x16 bit Multiplier using Vedic Mathematics," International Journal of Computer Applications, vol. 59, pp. 41-44, 2012.
B. Uslu and S. S. Erdem, "Versatile digit serial multipliers for binary extension fields," Computers & Electrical Engineering, vol. 46, pp. 29-45, 2015.
G. D. Sutter, J. Deschamps, and J. L. Imana, "Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations," IEEE Transactions onIndustrial Electronics, vol. 60, pp. 217-225, 2013.
M. Esmaeildoust, D. Schinianakis, H. Javashi, T. Stouraitis, and K. Navi, "Efficient RNS Implementation of Elliptic Curve Point Multiplication Over ," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, pp. 1545-1549, 2013.
H. Mahdizadeh and M. Masoumi, "Novel Architecture for Efficient FPGA Implementation of Elliptic Curve Cryptographic Processor Over ," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, pp. 2330-2333, 2013.
R. Azarderakhsh, K. U. Jarvinen, and M. Mozaffari-Kermani, "Efficient Algorithm and Architecture for Elliptic Curve Cryptography for Extremely Constrained Secure Applications," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, pp. 1144-1155, 2014.
H. Marzouqi, M. Al-Qutayri, and K. Salah, "Review of Elliptic Curve Cryptography processor designs," Microprocessors and Microsystems, vol. 39, pp. 97-112, 2015.
V. Kamalakannan and S. Tamilselvan, "Security Enhancement of Text Message Based on Matrix Approach Using Elliptical Curve Cryptosystem," Procedia Materials Science, vol. 10, pp. 489-496, 2015.
L. Marin, A. Jara, and A. S. Gomez, "Shifting primes: Optimizing elliptic curve cryptography for 16-bit devices without hardware multiplier," Mathematical and Computer Modelling, vol. 58, pp. 1155-1174, 2013.
S. Anjana, C. Pradeep, and P. Samuel, "Synthesize of High Speed Floating-point Multipliers Based on Vedic Mathematics," Procedia Computer Science, vol. 46, pp. 1294-1302, 2015.
A. Chatterjee and I. Sengupta, "Design of a high performance Binary Edwards Curve based processor secured against side channel analysis," VLSI Journal Integration, vol. 45, pp. 331-340, 6// 2012.
S. Rajagopalan, R. Amirtharajan, H. N. Upadhyay, and J. B. B. Rayappan, "Survey and analysis of hardware cryptographic and steganographic systems on FPGA," Journal of Applied Sciences, vol. 12, p. 201, 2012.
K. R. Kumar and R. Boda, "FPGA Implementation of Fast Elliptic Curve Cryptography using Itoh-Tsujii algorithm," Proceedings of ICETET, vol. 29, p. 30th, 2014.
D. Li and Y. Liu, "Development of security scheme on wireless sensor network based on Elliptic Curve Cryptography," 2015.
E. A. Abdulrahman and A. Reyhani-Masoleh, "New Regular Radix-8 Scheme for Elliptic Curve Scalar Multiplication without Pre-Computation," IEEE Transactions on Computers, vol. 64, pp. 438-451, 2015.
R. Azarderakhsh and A. Reyhani-Masoleh, "Parallel and High-Speed Computations of Elliptic Curve Cryptography Using Hybrid-Double Multipliers," IEEE Transactions on Parallel and Distributed Systems, vol. 26, pp. 1668-1677, 2015.
J.-W. Lee, S.-C. Chung, H.-C. Chang, and C.-Y. Lee, "Efficient power-analysis-resistant dual-field elliptic curve cryptographic processor using heterogeneous dual-processing-element architecture," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, pp. 49-61, 2014.
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